In order to develop and improve, semiconductor manufacturing processes more than those used conventionally, prototyping and evaluation are performed for a semiconductor device for testing, referred to as a TEG (Test Element Group) in which fixed patterns are formed. Characteristics of a realized TEG are evaluated, failure analysis is performed by a failure analysis device, feedback is provided to a semiconductor manufacturing process and to circuit design, and optimization of the semiconductor manufacturing process and circuit design is performed.
FIG. 1 is a planar view of a conventional TEG wiring pattern for resistor pattern evaluation. In FIG. 1, plural resistor patterns 108 are disposed in a resistor pattern region 107 between a measuring pad 101 and a measuring pad 102; these resistor patterns 108 are connected by inter-resistor-pattern wiring 120; and overall, the plural resistor patterns 108 are connected in series between the measuring pad 101 and the measuring pad 102. According to a pattern to be evaluated, various patterns, such as upper layer wiring, lower layer wiring, diffused resistors, contact wiring in which plural contacts are connected in series by the upper layer wiring and the lower layer wiring, are formed in the resistor pattern region 107. Here, these evaluation patterns are referred to generally as resistor patterns, but in a case where an evaluation pattern is itself a wire, a resistance value thereof is quite low.
Conventional TEG and failure analysis methods using TEG are described in Patent Documents 1 to 3, as below.
Patent Document 1 describes using a semiconductor device in which are arranged first and second comb-type wiring patterns laid out with comb-type portions engaged, and a third comb-type wiring pattern, being a wiring pattern laid out in a layer different from the first and second comb-type wiring patterns, extending in a direction orthogonal to the first and second comb-type wiring patterns, and the second comb-type wiring pattern and the third comb-type wiring pattern are connected by a plurality of vias, wherein by applying a voltage between the first comb-type wiring pattern and the third comb-type wiring pattern, and by inspecting a route of a current flowing from the first comb-type wiring pattern via the second comb-type wiring pattern to the third comb-type wiring pattern, a location of a short between the first comb-type wiring pattern and the second comb-type wiring pattern is narrowed down.
Furthermore, Patent Document 2 describes disposing a plurality of dummy wiring patterns between actual wiring patterns at a fine pitch, and arranging a separation distance between the actual wiring patterns such that it is possible to perform pattern analysis by an OBIRCH method, so as to perform defect analysis in fine pitch wiring where it is difficult to identify defect locations.
Additionally, Patent Document 3 describes a defect analysis system and a defect analysis method for a semiconductor device, in which, with regard to a plurality of wires having terminals arranged at each end, wire resistances between terminals of the same wire and between terminals of different wire are measured, a judgment is made as to whether or not there is a short between adjacent wire based on a wire resistance value, a short estimation position is estimated based on a wire resistance value, and in addition the short estimated position is observed.    [Patent Document 1]
JP Patent Kokai Publication No. JP-P2005-303162A    [Patent Document 2]
JP Patent Kokai Publication No. JP-P2005-191249A    [Patent Document 3]
JP Patent Kokai Publication No. JP-P2003-194889A